Processor performance has increased a thousand-fold over the past twenty years. Much of this increase is due to deeper pipelines, which enable greater exploitation of parallelism. Over the past several decades, pipeline depths have grown, allowing processors to exploit more and more parallelism, and to achieve higher and higher performance. However, the further use of parallelism in processors by increasing pipeline depths has become problematic. Critical loops within processors now present a significant and growing obstacle to further increases in pipelining. Critical loops are sections of logic that typically must evaluate in a single cycle to meet Instructions Per Cycle (IPC) performance goals. One such critical loop is the wakeup and select (i.e., dynamic instruction scheduling) logic.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.